1. Field of the Invention
The present invention relates to semiconductor devices, more particularly to a junction transistor.
2. Description of the Related Art
JP 2015-135844A discloses a lateral junction field effect transistor (JFET) exhibiting high breakdown voltage, the JFET including a drain region and an input pad connected to the drain region allocated in the middle of a circular planar pattern, and a plurality of source regions on the periphery of the circular planar pattern. JP 2008-153636A discloses a JFET having a structure similar to the structure disclosed in JP 2015-135844A, the JFET includes a resistor made of a polysilicon film, for example, and the resistor is delineated above an oxide film on a drift layer and connected in parallel to an input pad. The resistor has a function of detecting an input voltage (a brownout function).
For testing a surge withstand capability (SWC) for an electrostatic discharge (ESD) (hereinafter, referred to as an “SWC”) in a semiconductor device, two types of models are commonly used, which are a machine model (MM±) and a human body model (HBM±). The MM+ uses a relatively low voltage of approximately 200 volts. The JFET as disclosed in JP 2015-135844A and JP 2008-153636A can withstand the voltage level of the MM+ and therefore can be protected against the ESD surge.
As compared with the MM+, the HBM+ uses a relatively high voltage of approximately 1000 volts to 2000 volts. Source potential increases as a surge voltage applied to the JFET increases. The JFET disclosed in JP 2015-135844A is protected against the ESD surge until the surge voltage reaches the source breakdown voltage or the breakdown voltage of the circuit element connected to the source region to implement the starter circuit. Moreover, in the JFET disclosed in JP 2008-153636A, there is a difference in potential-transmission behavior with respect to the applied ESD surge of the HBM+ between the potential through the resistor used for the brownout function and the potential due to a depletion layer in silicon, and which leads to a potential difference in the oxide film below the resistor. The JFET disclosed in JP 2008-153636A is protected against the applied ESD surge of the HBM+ until the surge voltage reaches a level of the breakdown voltage of the oxide film. However, when the potential difference increases, the oxide film is damaged.
It is difficult to provide a space for arranging an element for protecting against the ESD surge in parallel to the JFET disclosed in JP 2015-135844A and JP 2008-153636A, since the JFET serving as a starter element itself is provided with the input pad. In order to improve the SWC, it is conceivable to increase the resistance by increasing a distance between the input pad and the source region and increasing a size of the device, so as to suppress the rise in source potential and the potential difference occurring in the oxide film. However, as the size of the device increases, the entire cost increases.